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[VHDL-FPGA-Verilog] m_sequence

Description: 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language description of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
Platform: | Size: 6144 | Author: 周青晖 | Hits:

[Other] mxulie

Description: m序列的verilog代码以及测试程序，希望对大家有用哦，花了时间写的-m sequence Verilog code, and test procedures in the hope of everyone Oh, it took time to write
Platform: | Size: 2048 | Author: 黄晓 | Hits:

[VHDL-FPGA-Verilog] m_seq_test_2

Description: 产生m序列的一个verilog程序，n=4.还有它在modelsim上的测试程序-a project generates m sequence and its test code
Platform: | Size: 223232 | Author: wa | Hits:

[VHDL-FPGA-Verilog] Design-exercise-M_sequence

Description: 通信系统电路设计练习： M序列编码/解码器的设计 作业的背景及训练目的 为了给通信专业的同学们提供一个设计实践的机会，在最短的时间段内掌握数字设计的动手能力，提高Verilog语言的使用能力，所以专门设计了这样一个难度适中的数字通信系统设计练习。本练习是根据工程实际问题提出的，但为了便于同学理解，对设计需求指标做了许多简化。希望同学们在设计范例和老师的指导下，一步一步地达到设计目标。期望同学们能在两至三周内，参考设计范例，独立完成自己的设计任务，在这一过程中学习用Verilog编写RTL代码和仿真验证用测试代码技术，以及用综合器进行综合的技术、并熟练掌握较复杂数字系统的多层次的仿真验证的方法，以逐步提高同学在设计工作中的自信心。-communication design exercise M_sequence
Platform: | Size: 141312 | Author: | Hits:

[VHDL-FPGA-Verilog] ss

Description: verilog语言编写的基于M序列的编解码设计-verilog language design M-sequence-based codec
Platform: | Size: 17408 | Author: 宋锴 | Hits:

[FlashMX] am29bdd160g

Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), amd 公司 2.5 V电压, flash存储器仿真读写verilog 模型。-16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory verilog model.
Platform: | Size: 20480 | Author: cmic | Hits:

[VHDL-FPGA-Verilog] M_code

Description: m序列实现,里面含verilog代码和教程，适合学习-m code
Platform: | Size: 155648 | Author: uodsi | Hits:

[VHDL-FPGA-Verilog] m_4_generater

Description: m序列发生器，verilog hdl语言 ，4位-m-sequence generator, verilog hdl language 4
Platform: | Size: 1024 | Author: 马俊汉 | Hits:

[VHDL-FPGA-Verilog] m_seq

Description: Verilog HDL 实现的4位二进制 16个m序列产生-Verilog HDL m_seq
Platform: | Size: 1944576 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] cmi

Description: 运用4阶m序列产生信号源 即消息码 用verilog编程实现cmi的产生-The use of fourth-order m-sequence generator source message code Verilog programming cmi generation
Platform: | Size: 248832 | Author: zyc | Hits:

[Communication] SDRAM50M

Description: 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
Platform: | Size: 4499456 | Author: 刘far | Hits:

[Books] caiyang

Description: verilog语言生成M伪随机序列，用quatus软件编译-verilog language generation M pseudo-random sequence
Platform: | Size: 2048 | Author: 周 | Hits:

[VHDL-FPGA-Verilog] shuzixinhao

Description: 使用verilog编程，实现m序列发生，m转化为曼彻斯特编码。已经过仿真，拥有vt文件。-Use verilog programming, the realization of m sequence, m into Manchester coding. Simulation, has been with vt.
Platform: | Size: 2473984 | Author: 谢华 | Hits:

[VHDL-FPGA-Verilog] mPsequences

Description: m序列信号发生，用verilog编写，在fpga上可实现-m sequences
Platform: | Size: 272384 | Author: catherine zhang | Hits:

[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
Platform: | Size: 16858112 | Author: YUKAI ZHANG | Hits:

[VHDL-FPGA-Verilog] m_xulie

Description: 在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。-In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.
Platform: | Size: 1024 | Author: 王子 | Hits:

[VHDL-FPGA-Verilog] RANGEN

Description: 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.
Platform: | Size: 119808 | Author: ai | Hits:

[VHDL-FPGA-Verilog] m_sequence_fpga

Description: 采用Verilog语言编写的伪随机序列——m序列，可用作通信系统输入数据源。-Use Verilog language- m sequence pseudo random sequence, and can be used as input data sources in communication system.
Platform: | Size: 388096 | Author: qiaofeng | Hits:

[ELanguage] bin_count

Description: i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
Platform: | Size: 28672 | Author: Nilesh panchal | Hits:

[VHDL-FPGA-Verilog] DIVIDER

Description: M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
Platform: | Size: 2048 | Author: HP | Hits:
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